The present invention relates to a thin film transistor used for a liquid crystal display of an active matrix system or the like. The invention also relates to methods for manufacturing a multilayer film structure and the thin film transistor.
The liquid crystal display of an active matrix system that uses a thin film transistor is constructed in a manner that a gate electrode (Y electrode) and a data electrode (X electrode) are disposed in a matrix form, and a liquid crystal is sealed in between a TFT array substrate having a thin film transistor (TFT) disposed at an intersection thereof and an opposite substrate laminated by keeping a gap with the TFT array substrate. The liquid crystal display can perform displaying by using the thin film transistor to control a voltage applied to the liquid crystal, and also by using an electro-optical effect provided by the liquid crystal.
Conventionally known thin film transistor structures include a top gate type (positive stagger type) and a bottom gate type (negative stagger type). A thin film transistor of the top gate type has a light shielding film formed on an insulating substrate such as a glass board, and an insulating film formed thereon, which is made of a silicon oxide SiOx, a silicon nitride SiNx or the like. On the insulating film, drain and source electrodes made of ITO (Indium and Tin Oxide) films are disposed by keeping a channel space. Then, an amorphous silicon film (a-Si film) is formed to cover the two electrodes, and a gate insulating film made of SiOx, SiNx or the like is formed on the a-Si film. On the gate insulating film, a gate electrode is provided. Accordingly, an island region called an a-Si island is formed. On the other hand, a thin film transistor of the bottom gate type has a gate electrode provided on an insulating substrate, and a gate oxide film and an amorphous silicon film (a-Si film) are provided on the gate electrode in this order. Then, source and drain electrodes are formed, and a protective film is formed thereon.
FIGS. 4(a) to 4(g) illustrate respective steps of manufacturing a conventional thin film transistor by taking an example of the bottom gate type. As a typical process of manufacturing the conventional thin film transistor, a 7 PEP (Photo Engraving Process) structure is available. In accordance with the 7 PEP structure, first in 1 PEP, as shown in FIG. 4(a), an alloy film made of tantalum (Ta) or molybdenum tantalum (MoW), or a metallic film made of aluminum (Al) is formed on a cleaned glass board 101 by sputtering, and a gate electrode 102 and a capacitor (Cs) electrode 103 are patterned. Then, in 2 PEP, as shown in FIG. 4(b), a gate insulating film 104 made of SiOx or SiNx is formed by a plasma CVD (Chemical Vapor Deposition) technology or the like. Subsequently, by plasma CVD, an a-Si film 105 as a semiconductor film and an etching protective film 106 made of SiNx are continuously laminated, and the etching protective film 106 is formed by patterning. Then, in 3 PEP, as shown in FIG. 4(c), a semiconductor layer (a-Si layer) is formed by patterning only a portion of the a-Si film 105 that will be a TFT.
Then, in 4 PEP, as shown in FIG. 4(d), a pixel electrode (transparent electrode) 107 is formed by sputtering an ITO film (Indium Tin Oxide film) as a transparent electrode on a portion to become a pixel electrode. On the other hand, in 5 PEP, as shown in FIG. 4(e), to form an electrode section of an storage capacitor (Cs), a part of the gate insulating film 104 on the Cs electrode 103 is subjected to patterning, and removed. Then, in 6 PEP, as shown in FIG. 4(f), a source electrode 108, a drain electrode 109 and a Cs electrode 110 are formed by sputtering and then patterning metal such as aluminum (Al) or titanium (Ti). Lastly, as shown in FIG. 4(g), a nitride film (SiNx) is grown by CVD to protect an element such as a TFT. Then, this film is subjected to patterning to form a protective film 111. A TFT is then completed by performing characteristic checking.
However, since the conventional 7 PEP structure requires a number of steps and the process itself becomes complex, manufacturing costs become high. In other words, investments are costly because of very high prices of forming the films using the complex PEP processes. For example, in the conventional TFT manufacturing process shown in FIG. 4, since all the patterning operations use resist exposure, an exposure device is necessary. Also, since the metallic layer is formed by sputtering, a sputtering device is necessary. Any of these devices is very high in price in the order of 500 to 800 million yen per unit, and has a plurality of layers. To meet a throughput requirement, several to several tens of these devices must be installed. The installation of the devices amounts to a considerable portion of investments in the order of several to several tens of billion yen, which is needed to prepare a new liquid crystal display line. Thus, improvements in the manufacturing process have been strongly demanded.
To improve the process, several technologies have conventionally been presented: e.g., Japanese Patent Laid-Open Hei 2 (1990)-232935, Patent Laid-Open Hei 2 (1990)-237039, Patent No. 2778133, Patent Laid-Open Hei 4 (1992)-309927. In accordance with these Publications, an electrode of conductive material is formed by plating, and the steps of vacuum deposition and photolithography are omitted. Thus, manufacturing costs can be reduced. For the purpose of improving the manufacturing process based on the foregoing 7 PEP structure, for example, in Japanese Patent Application Hei 11 (1999)-214603, the inventors already disclosed the technology to improve the manufacturing process based on the 4 PEP structure. In accordance with this technology, for example, in the TFT of a top gate type, by using a pattern of a gate electrode as a mask, one patterning step is carried out to continuously etch the gate electrode, a gate insulating film and an a-Si film. This invention is very effective in that the manufacturing process can be shortened.
The present invention was made in order to solve the foregoing technical problems.
It is an object of the invention to greatly improve a manufacturing process for a multilayer film structure of a thin film transistor or the like.
Another object of the invention is to reduce current leakage between electrodes by forming an offset region in a manufactured multilayer film structure.
Yet another object of the invention is to provide a multilayer film structure, where offset lengths of formed offset regions are uniform.
In order to achieve the foregoing objects, a thin film transistor of the present invention comprises: source and drain electrodes disposed at a specified interval on an insulating substrate; a semiconductor layer electrically couples the source and drain electrodes; a gate insulating film is disposed between the semiconductor layer and a gate electrode. The semiconductor layer and the gate insulating film have offset regions, which are located around the gate electrode but extend beyond the dimensions of the gate electrode. The drain electrode, source electrode, and/or gate electrode are formed by printing-and-plating.
In top-gate style TFTs, patterning of the semiconductor layer and the gate insulating film is preferably accomplished by plating a sacrificial layer on the gate electrode and subjecting the structure to an etchant that etches the gate insulating film and semiconductor layer and removes the sacrificial layer. Using plating to form the sacrificial layer enables widths of offset regions to be uniform (substantially equal), and is preferable because of its ability to properly prevent surface leakage between the gate electrode and the source/drain electrodes. In addition, the source and drain electrodes may be formed by printing-and-plating. The plated formation of these electrodes can eliminate the necessity of using a technology of photolithography, and is advantageous in that the process can be simplified, enables investment costs to be reduced more greatly. This reduces the costs for manufacturing the TFT structure.
The invention should not be limited to the structure of a top gate type as a thin film transistor structure. For example, it can also be applied to the structure of a bottom gate type thin film transistor. Also, it can be used in a laminated structure or in a contact or non-contact type structure.
A multilayer film structure of the present invention comprises: a first metal layer that is formed by printing-and-plating and disposed above a substrate; an insulating layer disposed between the first metal layer and a second metal layer formed by printing-and-plating.
Preferably, the insulating layer is patterned by plating a sacrificial layer on the second metal layer and subjecting the structure to an etchant that etches the insulating film and removes the sacrificial layer, thereby forming an offset region in the insulating film that extends beyond the dimensions of the second metal layer. Using plating to form the sacrificial layer enables the offset regions to be uniform (substantially equal), and is preferable because of its ability to properly prevent surface leakage between the first metal layer and the second metal layer. Also, the metallic layers can be easily formed.
Moreover, formation of the conductive layers of TFT devices and multilayer devices by printing-and-plating enables investment costs to be reduced greatly. As a result, costs for manufacturing such devices can be greatly reduced.